DTCO Layout R&D Engineer at imec – Define the Future of CMOS Technology

imec is hiring a DTCO Layout R&D Engineer to lead research into logic and SRAM integration beyond the 2nm node. This is a rare opportunity to influence the core of future CMOS technologies through design-technology co-optimization (DTCO).

🔍 Job Details

Detailed Blog Post

As CMOS technology races toward and beyond the 2nm node, imec offers a rare opportunity for innovators to join its cutting-edge Design Technology Co-Optimization (DTCO) research team. Located in the innovation capital of Leuven, Belgium, imec is looking for a DTCO Layout R&D Engineer who will help bridge the gap between process engineering and circuit design.

This role involves defining and validating design strategies for advanced logic and SRAM technologies, including nanosheet FETs, CFETs, and 2D FETs. You’ll work closely with lithography and process teams to translate device-level breakthroughs into layout-ready, manufacturable designs.

You’ll be hands-on with design rule creation, custom layout, DRC/LVS verification, parasitic extraction, and library characterization. Your contributions will directly impact imec’s global R&D collaborations and define the performance, power, and area metrics of next-generation chips.

Ideal candidates are experienced in CMOS layout, simulation, RTL and synthesis, and comfortable using EDA tools such as Virtuoso, Calibre, Spectre, and Liberate. A strong grasp of PDK development, scripting (TCL, Python), and automation is essential, along with the ability to work in a fast-paced, team-driven environment.

If you’re passionate about pushing the limits of chip design and want to influence global semiconductor innovation from the core, this role is made for you. imec supports your growth through its in-house imec.academy, multicultural environment, and performance-driven culture.

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